1. Field of the Invention
The present invention relates to an electrically erasable nonvolatile semiconductor memory (EEPROM) and a fabrication method thereof.
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM), which electrically performs data write-in and erasure, for example, has been known as a nonvolatile semiconductor memory (R. Shirota, ‘A Review of 256 Mbit NAND Flash Memories and NAND Flash Future Trend’, Nonvolatile Semiconductor Memory Workshop (NVSMW), 2000, p. 22-31). In such as EEPROM, especially a NAND type, a memory cell array is configured by deploying or locating memory cells at the respective intersections of horizontal word lines and vertical bit lines. A MOS transistor having a ‘stacked gate structure’ configured by stacking a floating gate (FG) and a control gate (CG), for example, is typically used as a memory cell.
It should be noted that Japanese Patent Application Laid-open No. 2002279788, for example, discloses a NAND cell-type EEPROM with certain structural characteristics. Memory cells are formed in each device region isolated by device isolation regions called shallow trench isolation (STI). Each memory cell has a stacked gate structure. Such a structure is characterized by an extended control gate used as a word line.